This invention relates generally to integrated circuit memories and more particularly to a ferroelectric nonvolatile random access memory.
The use of segmented plate lines is known in ferroelectric memory arrays. Segmented plate lines eliminate changes in the polarization state of memory cells coupled to inactive plate line segments, reducing fatigue and extending the useful operating life of the memory. Additionally, total power consumption of the memory array is reduced and the time required to transition a plate line segment is desirably reduced as compared to a non-segmented plate line.
Referring now to FIG. 1, a prior art memory cell array 10 having segmented plate lines includes a plurality of one transistor, one capacitor ferroelectric memory cells 24 arranged in rows and columns, a plurality of word lines labeled WL.sub.1, WL.sub.2, and WL.sub.N, a plurality of bit lines labeled BL1 through BL.sub.4, and BL.sub.5 through BL.sub.8, and plate line segments labeled PL.sub.11 through PL.sub.1N and PL.sub.21 through PL.sub.2N. A row of memory cells 24 includes a word line WL and the memory cells that are coupled to that word line. For example, word line WL.sub.1, and memory cells 24-24C and 24D-24G comprise a row of memory cells. The word lines WL.sub.1, WL.sub.2, through WL.sub.N are disposed substantially parallel to one another in one direction. A column of memory cells includes a bit line and the memory cells that are coupled to the bit line. For example, bit line BL.sub.4, and memory cells 24C, 24H, through 24K comprise a column of memory cells. The bit lines BL.sub.1 through BL.sub.4 and BL.sub.5 through BL.sub.8 are disposed substantially parallel to one another, and perpendicular to the word lines. Each one transistor, one capacitor memory cell includes an N-channel access transistor and a ferroelectric capacitor. For example, memory cell 24 includes access transistor 28 and ferroelectric capacitor 30. Access transistor 28 has a first current node connected to bit line BL.sub.1, a second current node, and a control or gate node connected to word line WL.sub.1. Ferroelectric capacitor 30 has a first plate electrode connected to the second current node of access transistor 28, and a second plate electrode connected to plate line segment PL.sub.11. In the one transistor, one capacitor memory cell arrangement shown in array 10 of FIG. 1, bit lines BL.sub.1 through BL.sub.4 and BL.sub.5 through BL.sub.8 are coupled to sense amplifiers (not shown in FIG. 1) for detection of the charge liberated from polling the ferroelectric memory cells 24. The sense amplifiers, in turn, are also coupled to dummy or reference cells (also not shown in FIG. 1) for establishing a reference charge level that determines whether the charge on the bit lines will be resolved into a logic one or a logic zero level. It should be noted that the entire array 10 could be reconfigured with two transistor, two capacitor ferroelectric memory cells such as memory cell 26. Each two transistor, two capacitor memory cell includes two N-channel access transistors and two ferroelectric capacitors. For example, memory cell 26 includes access transistors 28A and 28B, and ferroelectric capacitors 30A and 30B. Access transistor 28A has a first current node connected to bit line BL.sub.1, a second current node, and a control or gate node connected to word line WL.sub.2. Ferroelectric capacitor 30A has a first plate electrode connected to the second current node of access transistor 28A, and a second plate electrode connected to plate line segment PL.sub.12. Access transistor 28B has a first current node connected to bit line BL.sub.2, a second current node, and a control or gate node connected to word line WL.sub.2. Ferroelectric capacitor 30B has a first plate electrode connected to the second current node of access transistor 28B, and a second plate electrode connected to plate line segment PL.sub.12. In the two transistor, two capacitor array configuration, bit lines BL1 through BL4 and BL5 through BL8 are coupled to sense amplifiers (not shown in FIG. 1), without the use of dummy or reference cells. The sense amplifiers resolve a valid logic state by comparing the charge on the two bit lines coupled to the memory cell, e.g. BL.sub.1 and BL.sub.2.
A plate line segment is coupled to a predetermined number of memory cells. In FIG. 1, four memory cells are shown coupled to each plate line segment. However, the number of memory cells coupled to a plate line segment is not significant, and may be different in other embodiments depending on the size of the array, data organization, etc. Each plate line segment is coupled to a drive line by a single NMOS coupling transistor. For example, coupling transistor 12 has a first current node connected to plate clock line PLCLK.sub.1, a second current node connected to plate line segment PL.sub.11, and a control or gate node connected to word line WL.sub.1. Memory cells 24-24C are coupled to plate line segment PL.sub.11. Coupling transistors 14 and 16 provide the plate line drive signal for plate line segments PL.sub.12 and PL.sub.1N, respectively. Similarly, coupling transistors 18, 20, and 22 provide the plate line drive signal for plate line segments PL.sub.21, PL.sub.22, and PL.sub.2N, respectively. Representative memory cells 24D-24G are coupled to plate line segment PL.sub.21.
In the segmented plate line array embodiment of FIG. 1 it is important to note that the voltage of the plate line signal for each of the plate line segments is equal to approximately the voltage of the plate line clock signal PLCLK (typically the power supply voltage, Vdd, of either 5 volts or 3.3 volts) minus a threshold voltage (VTN) drop across the corresponding NMOS drive transistors 12-22. For optimum performance at any operating voltage, it is desirable that the full PLCLK voltage be applied to the ferroelectric memory cells coupled to the plate line segments. It is even more important to apply the full PLCLK voltage to the plate line segments at low operating voltages. For reliable low power supply voltage operations, for example 3.3 volts, it is necessary to completely eliminate the V.sub.TN drop presented by coupling transistors 12-22.
Previous designs for eliminating or reducing the V.sub.TN drop of the coupling transistor have involved the use of P-channel transistors, complementary word lines, or boosted word lines. Many of the designs are impractical because of the penalty of greatly increased die size and circuit complexity.
Referring now to FIG. 2, a self-bootstrapping circuit 40 sometimes used in DRAM ("Dynamic Random Access Memory") and other memory applications for driving word lines to the full rail voltage. Circuit 40 has not been previously adapted for use in driving plate line segments in ferroelectric memory circuits. Circuit 40 includes a first NMOS transistor 32 having a first current node coupled to a low voltage word line enable signal WLEN at node 36, a gate coupled to a source of supply voltage (the rail voltage), and a second current node labeled WL'. A second NMOS transistor 34 has a first current node coupled to the word line WL at node 39, a second current node coupled to a word clock line WLCLK at node 38, and a gate coupled to the second current node WL' of the first NMOS transistor 32.
What is desired is a segmented plate line ferroelectric memory array having NMOS-only, layout-compact plate line segment drivers that will impress the full PLCLK voltage on each plate line segment, driving the segment to the full available Vdd rail voltage.